High Data Rate Pipelined Adaptive Viterbi Decoder Implementation
نویسندگان
چکیده
This paper presents a pipelined Adaptive Viterbi algorithm of rate 1⁄2 convolutional coding with a constraint length K = 3 which is designed in a reconfigurable hardware to take full advantage of algorithm parallelism, specialization and the throughput rate. In present work, the hardware implementation of the pipelined Adaptive Viterbi algorithm is performed using FPGA processor (Spartan-3AN starter Field Programmable Gate Array (FPGA) kit), and ModelSim simulation results are performed to ensure that the implemented scheme satisfy the design specification. On the other hand, processing time, power consumption, and design capacity should be studied well for real time implementation.
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